1. Field of the Invention
The present invention relates to a packet disassembler used in communication where there is no time transparency in the timing between packet assembly and disassembly, which packet disassembler has a plurality of buffers of a fixed length in which disassembly of packets is performed, and more particularly, to a packet disassembler which is suitably used in a controlling unit of an asynchronous transfer mode (ATM) switching system.
2. Description of the Related Art
Packet communication requires dividing a transmission frame into packets of a fixed length (which packets will be called "cells", and which division function will be called the cell-assembling function, hereinafter), disassembling cells, and then assembling them into a frame (which function is called the cell-disassembling function, hereinafter). In the cell-assembling and cell-disassembling functions, a buffer plays an important role. ATM communication is carried out using ATM cells.
Explanation will be made as to two types of prior art arrangements of buffers for implementing the cell-disassembling function.
In one type of prior art arrangement, a packet disassembler has fixed-length buffers having a length equal to or more than the length of a frame for which input ATM cells are disassembled for each connection identifier (VCI) indicative of connection therebetween or a multiplexing identifier (MID).
The plurality of fixed-length buffers are used as work buffers for the cell-disassembling operation, and writing is controlled on the basis of the connection identifier and multiplexing identifier received from an ATM layer so that the information fields of the ATM Cells having the same VCI or MID are assembled within one of the fixed-length buffers allocated to the connection identifier. The completion of the assembling operation is detected by a segment type (ST) field within the ATM cell and the assembled frame is read out and passed to an upper protocol layer.
In the other type of prior art arrangement, the buffers are of a short length corresponding to the size of the information field of the ATM cell to be assembled, and a releasable region having the short buffer is provided so that the short buffer is shared with the different connection identifiers or the different multiplexing identifiers on the connections.
The information fields of the input ATM cells are written in the releasable short buffer, and on the basis of the connection identifier or multiplexing identifier on the same connection received from an ATM layer, the information fields of the ATM cells having the same VCI or MID are assembled.
In the first arrangement in which the buffers are arranged to have respectively a long fixed length equal to or more than the maximum length of frames to be disassembled, when a particular connection is frequently used, its buffer operating efficiency becomes low. The second arrangement is designed to solve the above problem in the first arrangement and to increase memory operating efficiency by utilizing a fact that a buffer is usually made up of a memory and thus the buffer operating efficiency is equivalent to the memory operating efficiency.
However, the arrangement of the first and second buffers has a disadvantage that, since one of the buffers is selected on the basis of the connection identifier or multiplexing identifier on the same connection to be used as a buffer fixed to the identifier, even when the assembling of the frame for the identifier is completed, the next assembling of the frame for the same identifier cannot be carried out until the upper-level layer processor accepts the frame.
Assume, for example, that nine cells A1 to A9 having an identifier `a`, three cells B1 to B3 having an identifier `b` and 3 cells C1 to C3 having an identifier `c` are sequentially input and it is desired to disassemble them with use of first and second fixed-length buffers each having a length corresponding to about three cells. Then, since the first fixed-length buffer is fixedly allocated to the identifier `a`, it is impossible to disassemble the cell A4 having the identifier `a`, so long as an information signal indicative of the completion of the cell-disassembling operation of the cells A1 to A3 having the same identifier `a` is not received by the upper-level processor.
This requires the processing ability of the upper layer processor to be increased to such an extent that the reception of the frame can be within the minimum arrival interval of the fixed-length packets.